The FBER values are set for the life of the technology so, we needed to make the right set of trade-offs. We always produce better materials with lower loss characteristics but, once we make a target FBER and deploy the FEC/CRC accordingly, that does not change over time. For longer channels we can deploy Retimers.īased on our experience over the last two decades, channels always improve over time. Based on our analysis, we are confident of securing the existing channel reach to 1E-6 FBER. If the FBER was relaxed we would need a networking style FEC, even if we have the retry, to keep the retry probability less than 1E-5. Another point to note is that using BER would be about an order of magnitude worse than the FBER, due to burst errors in a Lane as well as Lane to Lane correlation.

As mentioned in the presentation, 10 -6 is a critical number to meet the latency requirement of FEC and Cyclic Redundancy Check (CRC) to be less than 2ns and reducing the bandwidth overhead in line with a less than 2% impact. We have conducted extensive studies before settling on the 10 -6 First Bit Error Rate (FBER). Will a higher Bit Error Rate (BER) such as 10 -4 provide more channel length?.This blog provides detailed answers to questions about FEC that were asked during the PCIe 6.0 Specification webinar. PCIe 6.0 technology uses a unique method to achieve low-latency through a combination of relatively lower First Bit Error Rate (FBER) 10 -6 combined with a lightweight, low-latency FEC to complete the initial correction. If a FLIT fails the CRC check, it is eventually corrected through the Link Layer Retry mechanism of PCIe. A receiver uses the FEC to correct any errors in a FLIT after which it applies the CRC check on the 250 Bytes that are protected by the CRC. FEC operates on the principle of sending redundant data that can be deployed to correct some errors at the Receiver while CRC is an error detection code used to detect errors. The 250 bytes of payload and CRC are protected by 6 Bytes of FEC. Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC. The PCI Express® (PCIe®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). By Debendra Das Sharma, PCI-SIG® Board Member

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